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Design Verification Engineer
| Dyddiad hysbysebu: | 25 Gorffennaf 2024 |
|---|---|
| Oriau: | Llawn Amser |
| Dyddiad cau: | 24 Awst 2024 |
| Lleoliad: | United Kigndom |
| Gweithio o bell: | Yn gyfan gwbl o bell |
| Cwmni: | SKAAR TECH LTD |
| Math o swydd: | Cytundeb |
| Cyfeirnod swydd: |
Crynodeb
Design Verification: Common responsibilities
Create coverage driven verification plan document.
Create UVM verification environment.
Verify CPU connectivity to IP blocks (using ASM boot, and C code, GNU toolchain)
The tasks will include writing test plans, defining test methodologies, developing test benches, writing testcases, completing functional verification and closing coverage for all the agreed design blocks in the SoCs/Subsystems
Run regressions, debug test failures and file bug report as needed.
Develop tests to meet functional coverage and code coverage requirements defined for the project, based on analysis of coverage gaps.
Provide verification report as needed to show all implemented tests passing on the RTL.
Methodologies will include a mix of design checks, verification techniques using simulators and emulators: UVM, formal, Verilog/System Verilog based testbenches and C, System Verilog, UVM based testcases
No visa will be sponsored for the role
Rate – upto GBP 75/hour (Insider IR35)
Contract duration – 6 months to 1 year
Create coverage driven verification plan document.
Create UVM verification environment.
Verify CPU connectivity to IP blocks (using ASM boot, and C code, GNU toolchain)
The tasks will include writing test plans, defining test methodologies, developing test benches, writing testcases, completing functional verification and closing coverage for all the agreed design blocks in the SoCs/Subsystems
Run regressions, debug test failures and file bug report as needed.
Develop tests to meet functional coverage and code coverage requirements defined for the project, based on analysis of coverage gaps.
Provide verification report as needed to show all implemented tests passing on the RTL.
Methodologies will include a mix of design checks, verification techniques using simulators and emulators: UVM, formal, Verilog/System Verilog based testbenches and C, System Verilog, UVM based testcases
No visa will be sponsored for the role
Rate – upto GBP 75/hour (Insider IR35)
Contract duration – 6 months to 1 year